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authorKrzysztof Kozlowski <krzk@kernel.org>2019-06-21 20:02:02 +0200
committerKrzysztof Kozlowski <krzk@kernel.org>2019-06-24 20:03:42 +0200
commit4a7bc07f5c04219067b328a3179bd3233fb0b7cd (patch)
treea386612144dfe284107cdbf015ce43f080fa450d /arch/arm/boot/dts/exynos3250.dtsi
parent8b388cee66350f2dd8e77afb9eab798ed5c796e9 (diff)
ARM: dts: exynos: Add GPU/Mali 400 node to Exynos3250
Add nodes for GPU (Mali 400) to Exynos3250. This is still limited and not tested: 1. No dynamic voltage and frequency scaling, 2. Not sure what to do with CLK_G3D clock responsible for gating entire IP block (it is now being disabled as unused). Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/exynos3250.dtsi')
-rw-r--r--arch/arm/boot/dts/exynos3250.dtsi33
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 8ce3a7786b19..c17870a54acf 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -126,6 +126,39 @@
};
};
+ gpu: gpu@13000000 {
+ compatible = "samsung,exynos4210-mali", "arm,mali-400";
+ reg = <0x13000000 0x10000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1",
+ "pp2",
+ "ppmmu2",
+ "pp3",
+ "ppmmu3",
+ "pmu";
+ clocks = <&cmu CLK_G3D>,
+ <&cmu CLK_SCLK_G3D>;
+ clock-names = "bus", "core";
+ power-domains = <&pd_g3d>;
+ status = "disabled";
+ /* TODO: operating points for DVFS, assigned clock as 134 MHz */
+ };
+
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,