diff options
| author | Krzysztof Kozlowski <k.kozlowski@samsung.com> | 2016-09-04 13:04:15 +0200 |
|---|---|---|
| committer | Krzysztof Kozlowski <k.kozlowski@samsung.com> | 2016-09-16 13:32:09 +0200 |
| commit | f7061ffb44116490f282f130a220ca2d10849248 (patch) | |
| tree | 08062cf65df40e7ff68dea932e647c7d34994653 /arch/arm/boot/dts/exynos4210-pinctrl.dtsi | |
| parent | a2f2bc384e8df20b881625e6a92726d5b9f39d6b (diff) | |
ARM: dts: exynos: Fix mismatched value for SD4 pull up/down configuration on exynos4210
The pinctrl pull up/down register on exynos4210 is 2-bit wide for each
pin and it accepts only values of 0, 1 and 3. The pins sd4-bus-width8
were configured with value of 4. The driver does not validate the value
so this overflow effectively set a bit 1 in adjacent pins thus
configuring them to pull down.
The author's intention was probably to set drive strength of 4x. All
other bus-widths pins are configured with pull up and drive strength of
4x. Fix this one with same pattern.
Fixes: 87711d8c7c70 ("ARM: dts: Add pinctrl node entries for SAMSUNG EXYNOS4210 SoC")
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/exynos4210-pinctrl.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/exynos4210-pinctrl.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi index 8046340e50ac..d9b6d25e4abe 100644 --- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi @@ -649,7 +649,7 @@ sd4_bus8: sd4-bus-width8 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <4>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; |