diff options
author | Ingo Molnar <mingo@kernel.org> | 2019-12-25 10:41:37 +0100 |
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committer | Ingo Molnar <mingo@kernel.org> | 2019-12-25 10:41:37 +0100 |
commit | 1e5f8a308551b9816588e12bb795aeadebe37c4a (patch) | |
tree | bd71fc796fed24a3b7cc99df4a1d1bdaecc2b387 /arch/arm/boot/dts/exynos4412.dtsi | |
parent | a5e37de90e67ac1072a9a44bd0cec9f5e98ded08 (diff) | |
parent | 46cf053efec6a3a5f343fead837777efe8252a46 (diff) |
Merge tag 'v5.5-rc3' into sched/core, to pick up fixes
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/exynos4412.dtsi')
-rw-r--r-- | arch/arm/boot/dts/exynos4412.dtsi | 25 |
1 files changed, 8 insertions, 17 deletions
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index d20db2dfe8e2..5022aa574b26 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -188,7 +188,7 @@ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; }; - sysram@2020000 { + sram@2020000 { compatible = "mmio-sram"; reg = <0x02020000 0x40000>; #address-cells = <1>; @@ -206,7 +206,7 @@ }; }; - pd_isp: isp-power-domain@10023ca0 { + pd_isp: power-domain@10023ca0 { compatible = "samsung,exynos4210-pd"; reg = <0x10023CA0 0x20>; #power-domain-cells = <0>; @@ -243,25 +243,16 @@ clock-names = "aclk200", "aclk400_mcuisp"; }; - mct@10050000 { + timer@10050000 { compatible = "samsung,exynos4412-mct"; reg = <0x10050000 0x800>; - interrupt-parent = <&mct_map>; - interrupts = <0>, <1>, <2>, <3>, <4>; clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; clock-names = "fin_pll", "mct"; - - mct_map: mct-map { - #interrupt-cells = <1>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = - <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>, - <1 &combiner 12 5>, - <2 &combiner 12 6>, - <3 &combiner 12 7>, - <4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>; - }; + interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <&combiner 12 5>, + <&combiner 12 6>, + <&combiner 12 7>, + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>; }; watchdog: watchdog@10060000 { |