diff options
| author | Guillaume Tucker <guillaume.tucker@collabora.com> | 2020-08-10 13:22:07 +0100 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzk@kernel.org> | 2020-08-17 20:08:38 +0200 |
| commit | 91b440ed2542510ef33ede55c12465b61c8acfa6 (patch) | |
| tree | cb66f3f3462934a39a72ded62023366cc81d0758 /arch/arm/boot/dts/exynos4412.dtsi | |
| parent | a084c9d2042d43f0b7b514d040e635d8b1fb643a (diff) | |
ARM: dts: exynos: add prefetch properties for L2C-310 cache
Add the devicetree properties to enable instruction and data prefetch
on exynos4210 and exynos4412 which use the L2C-310 cache. No other
Exynos chip appears to be using this L2 cache hardware.
This follows the default bits being set in the l2c_aux_val register
for the Exynos platform, which can now be cleared as a result.
Signed-off-by: Guillaume Tucker <guillaume.tucker@collabora.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/exynos4412.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/exynos4412.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 7002832eb4c0..c74b1be12671 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -218,6 +218,8 @@ reg = <0x10502000 0x1000>; cache-unified; cache-level = <2>; + prefetch-data = <1>; + prefetch-instr = <1>; arm,tag-latency = <2 2 1>; arm,data-latency = <3 2 1>; arm,double-linefill = <1>; |