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authorKrzysztof Kozlowski <krzk@kernel.org>2020-12-10 22:25:24 +0100
committerKrzysztof Kozlowski <krzk@kernel.org>2021-03-07 20:56:17 +0100
commitf6368c60561370e4a92fac22982a3bd656172170 (patch)
tree56cf411fc6b6046a27be543019072849bd397758 /arch/arm/boot/dts/exynos5250-smdk5250.dts
parentfbe9c9bb2e929865500a0985735f81c0142accad (diff)
ARM: dts: exynos: correct PMIC interrupt trigger level on SMDK5250
The Maxim PMIC datasheets describe the interrupt line as active low with a requirement of acknowledge from the CPU. Without specifying the interrupt type in Devicetree, kernel might apply some fixed configuration, not necessarily working for this hardware. Additionally, the interrupt line is shared so using level sensitive interrupt is here especially important to avoid races. Fixes: 47580e8d94c2 ("ARM: dts: Specify MAX77686 pmic interrupt for exynos5250-smdk5250") Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20201210212534.216197-8-krzk@kernel.org
Diffstat (limited to 'arch/arm/boot/dts/exynos5250-smdk5250.dts')
-rw-r--r--arch/arm/boot/dts/exynos5250-smdk5250.dts2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 8b5a79a8720c..39bbe18145cf 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -134,7 +134,7 @@
compatible = "maxim,max77686";
reg = <0x09>;
interrupt-parent = <&gpx3>;
- interrupts = <2 IRQ_TYPE_NONE>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&max77686_irq>;
#clock-cells = <1>;