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authorKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>2021-07-31 11:24:06 +0200
committerKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>2021-08-05 09:24:00 +0200
commitfa0c56dbc3a1b116d280c3a3a97052ea38e4ea2b (patch)
treefc8286d251422ad951c72bc39f704ba740847a16 /arch/arm/boot/dts/exynos5260.dtsi
parentfc6d5c9953757c61042676db9bb32ecd7af958f3 (diff)
ARM: dts: exynos: add CPU topology to Exynos5260
Describe Exynos5260 CPU topology. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20210731092409.31496-5-krzysztof.kozlowski@canonical.com
Diffstat (limited to 'arch/arm/boot/dts/exynos5260.dtsi')
-rw-r--r--arch/arm/boot/dts/exynos5260.dtsi38
1 files changed, 32 insertions, 6 deletions
diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi
index 973448c4ad93..52fa211525ce 100644
--- a/arch/arm/boot/dts/exynos5260.dtsi
+++ b/arch/arm/boot/dts/exynos5260.dtsi
@@ -34,42 +34,68 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu2>;
+ };
+ core1 {
+ cpu = <&cpu3>;
+ };
+ core2 {
+ cpu = <&cpu4>;
+ };
+ core3 {
+ cpu = <&cpu5>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x0>;
cci-control-port = <&cci_control1>;
};
- cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x1>;
cci-control-port = <&cci_control1>;
};
- cpu@100 {
+ cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
cci-control-port = <&cci_control0>;
};
- cpu@101 {
+ cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x101>;
cci-control-port = <&cci_control0>;
};
- cpu@102 {
+ cpu4: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x102>;
cci-control-port = <&cci_control0>;
};
- cpu@103 {
+ cpu5: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x103>;