diff options
| author | Ingo Molnar <mingo@kernel.org> | 2014-07-16 15:10:07 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2014-07-16 15:10:07 +0200 |
| commit | d26fad5b38e1c4667d4f2604936e59c837caa54d (patch) | |
| tree | 04b524a69a0129c181567445bff18847a1b44721 /arch/arm/boot/dts/exynos5420.dtsi | |
| parent | e720fff6341fe4b95e5a93c939bd3c77fa55ced4 (diff) | |
| parent | 1795cd9b3a91d4b5473c97f491d63892442212ab (diff) | |
Merge tag 'v3.16-rc5' into sched/core, to refresh the branch before applying bigger tree-wide changes
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/exynos5420.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/exynos5420.dtsi | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index e38532271ef9..15957227ffda 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -167,7 +167,7 @@ compatible = "samsung,exynos5420-audss-clock"; reg = <0x03810000 0x0C>; #clock-cells = <1>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>, <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; }; @@ -260,6 +260,9 @@ mfc_pd: power-domain@10044060 { compatible = "samsung,exynos4210-pd"; reg = <0x10044060 0x20>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>, + <&clock CLK_MOUT_USER_ACLK333>; + clock-names = "oscclk", "pclk0", "clk0"; }; disp_pd: power-domain@100440C0 { |