diff options
| author | Krzysztof Kozlowski <krzk@kernel.org> | 2020-06-26 10:06:37 +0200 |
|---|---|---|
| committer | Wei Xu <xuwei5@hisilicon.com> | 2020-07-17 10:09:21 +0800 |
| commit | 5720fcdc2e5af74e51c5e3102fcefd9fb061a666 (patch) | |
| tree | e731fbe3a9586929acaf748fc86f9e7719857584 /arch/arm/boot/dts/hisi-x5hd2.dtsi | |
| parent | b3a9e3b9622ae10064826dccb4f7a52bd88c7407 (diff) | |
ARM: dts: hisilicon: Align L2 cache-controller nodename with dtschema
Fix dtschema validator warnings like:
l2-cache: $nodename:0: 'l2-cache' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Diffstat (limited to 'arch/arm/boot/dts/hisi-x5hd2.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/hisi-x5hd2.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index 696e6982a688..3ee7967c202d 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -381,7 +381,7 @@ interrupts = <1 13 0xf01>; }; - l2: l2-cache { + l2: cache-controller { compatible = "arm,pl310-cache"; reg = <0x00a10000 0x100000>; interrupts = <0 15 4>; |