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authorShawn Guo <shawn.guo@linaro.org>2013-07-11 13:58:36 +0800
committerShawn Guo <shawn.guo@linaro.org>2013-08-22 23:29:11 +0800
commitc56009b2f6134e5943a03cf26e4d7fce9745d56b (patch)
treebd792350bb8bea866bf45c36ec18df64e8c9b5d2 /arch/arm/boot/dts/imx6q-sabrelite.dts
parent51056d9cff64ba1347a20476c840e943576f0283 (diff)
ARM: dts: imx: share pad macro names between imx6q and imx6dl
The imx6q and imx6dl are two pin-to-pin compatible SoCs. The same board design can work with either chip plugged into the socket, e.g. sabresd and sabreauto boards. We currently define pin groups in imx6q.dtsi and imx6dl.dtsi respectively because the pad macro names are different between two chips. This brings a maintenance burden on having the same label point to the same pin group defined in two places. The patch replaces prefix MX6Q_ and MX6DL_ with MX6QDL_ for both SoCs pad macro names. Then the pin groups becomes completely common between imx6q and imx6dl and can just be moved into imx6qdl.dtsi, so that the long term maintenance of imx6q/dt pin settings becomes easier. Unfortunately, the change brings some dramatic diff stat, but it's all about DTS file, and the ultimate net diff stat is good. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6q-sabrelite.dts')
-rw-r--r--arch/arm/boot/dts/imx6q-sabrelite.dts16
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 6a000666c147..38b8aeac5c56 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -91,14 +91,14 @@
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
- MX6Q_PAD_NANDF_D6__GPIO2_IO06 0x80000000
- MX6Q_PAD_NANDF_D7__GPIO2_IO07 0x80000000
- MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000
- MX6Q_PAD_EIM_D22__GPIO3_IO22 0x80000000
- MX6Q_PAD_EIM_D23__GPIO3_IO23 0x80000000
- MX6Q_PAD_SD3_DAT5__GPIO7_IO00 0x80000000
- MX6Q_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0
- MX6Q_PAD_GPIO_0__CCM_CLKO1 0x80000000
+ MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000
+ MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000
+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
+ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000
+ MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x80000000
>;
};
};