diff options
| author | Andreas Kemnade <andreas@kemnade.info> | 2021-01-13 00:15:46 +0100 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2021-01-18 15:07:16 +0800 |
| commit | b34af2eef6ac78c8734879fa2f8fadb85cd1145f (patch) | |
| tree | acf4cd0390aa646dbc9ca0e6e960d3e35aa5c5d5 /arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts | |
| parent | 4dec146131c592196df579a321b9d6ec7c41d7cd (diff) | |
ARM: dts: imx6sl-tolino-shine2hd: add second uart
There is another uart next to the console uart used by vendor uboot and
kernel, enable it and document its location.
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts')
| -rw-r--r-- | arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts b/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts index e17c75c360f2..6ea5f918d059 100644 --- a/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts +++ b/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts @@ -340,7 +340,6 @@ MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x79 MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79 MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x79 - MX6SL_PAD_KEY_ROW6__GPIO4_IO05 0x79 >; }; @@ -400,6 +399,13 @@ >; }; + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1b0b1 + MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x1b0b1 + >; + }; + pinctrl_usbotg1: usbotg1grp { fsl,pins = < MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 @@ -549,6 +555,13 @@ status = "okay"; }; +&uart4 { + /* TP198, next to J4, SMD pads */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc2>; |