diff options
| author | Peng Fan <peng.fan@nxp.com> | 2020-03-11 17:02:06 +0800 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2020-03-16 09:18:29 +0800 |
| commit | f5d35d87ef061172a25252b2b5402c972b16d3be (patch) | |
| tree | 1cd6ec8d5014a25e6ccd3efcaba1fddcbe8ec20f /arch/arm/boot/dts/imx6sl.dtsi | |
| parent | 98670a0bb0ef14bbb3df8542e59e0e6106c0ba53 (diff) | |
ARM: dts: imx: add nvmem property for cpu0
Add nvmem related property for cpu0, then nvmem API could be used
to read cpu speed grading to avoid directly read OCOTP registers
mapped which could not handle defer probe.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6sl.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6sl.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index c6141ed87e4d..8230b45057a1 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -74,6 +74,8 @@ arm-supply = <®_arm>; pu-supply = <®_pu>; soc-supply = <®_soc>; + nvmem-cells = <&cpu_speed_grade>; + nvmem-cell-names = "speed_grade"; }; }; @@ -953,6 +955,12 @@ compatible = "fsl,imx6sl-ocotp", "syscon"; reg = <0x021bc000 0x4000>; clocks = <&clks IMX6SL_CLK_OCOTP>; + #address-cells = <1>; + #size-cells = <1>; + + cpu_speed_grade: speed-grade@10 { + reg = <0x10 4>; + }; }; audmux: audmux@21d8000 { |