diff options
| author | Stefan Riedmueller <s.riedmueller@phytec.de> | 2019-07-09 09:19:20 +0200 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2019-07-23 13:38:25 +0800 |
| commit | 458264157b1044d242afa163ac407dc55fa8134e (patch) | |
| tree | b5adaf6cc06b06838ad0c5dbdb469e4d07c1bc57 /arch/arm/boot/dts/imx6ul-phytec-segin.dtsi | |
| parent | e37816bf9114ee1604a1511f7b4155b753ab36b9 (diff) | |
ARM: dts: imx6ul: segin: Reduce eth drive strength
Reduce the drive strength for the MDC, MDIO and TX pins of FEC1 and FEC2
on the phyBOARD-Segin to improve signal quality and EMC. Also disable
internal pull-ups on the MDC and MDIO pins.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6ul-phytec-segin.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6ul-phytec-segin.dtsi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi index 78425c3290a1..28ba3a4c4c74 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi @@ -230,10 +230,10 @@ MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010 >; }; |