diff options
| author | Sébastien Szymanski <sebastien.szymanski@armadeus.com> | 2019-07-24 14:06:22 +0200 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2019-10-02 09:09:48 +0800 |
| commit | 5460ab061e7a127c84622a5189bce7aebc921dea (patch) | |
| tree | 33cb558ae4fada3a58f3773c823ee06ba104c689 /arch/arm/boot/dts/imx6ull-opos6uldev.dts | |
| parent | 54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c (diff) | |
ARM: dts: opos6ul/opos6uldev: rework device tree to support i.MX6ULL
Rework the device trees of the OPOS6UL and OPOS6ULDev boards to support
the OPOS6UL SoM with an i.MX6ULL SoC. The device trees are now as
following:
- imx6ul-imx6ull-opos6ul.dtsi
common for both i.MX6UL and i.MX6ULL OPOS6UL SoM.
- imx6ul-opos6ul.dtsi
for i.MX6UL OPOS6UL SoM. It includes imx6ul.dtsi and
imx6ul-imx6ull-opos6ul.dtsi.
- imx6ull-opos6ul.dtsi
for i.MX6ULL OPOS6UL SoM. It includes imx6ull.dtsi and
imx6ul-imx6ull-opos6ul.dtsi.
- imx6ul-imx6ull-opos6uldev.dtsi
OPOS6ULDev base device tree.
- imx6ul-opos6uldev.dts
OPOS6ULDev board with an i.MX6UL OPOS6UL SoM. It includes
imx6ul-opos6ul.dtsi and imx6ul-imx6ull-opos6uldevdtsi.
- imx6ull-opos6uldev.dts
OPOS6ULDev board with an i.MX6ULL OPOS6UL SoM. It includes
imx6ull-opos6ul.dtsi and imx6ul-imx6ull-opos6uldevdtsi.
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6ull-opos6uldev.dts')
| -rw-r--r-- | arch/arm/boot/dts/imx6ull-opos6uldev.dts | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6ull-opos6uldev.dts b/arch/arm/boot/dts/imx6ull-opos6uldev.dts new file mode 100644 index 000000000000..198fdb72641b --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-opos6uldev.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright 2019 Armadeus Systems <support@armadeus.com> + +/dts-v1/; +#include "imx6ull-opos6ul.dtsi" +#include "imx6ul-imx6ull-opos6uldev.dtsi" + +/ { + model = "Armadeus Systems OPOS6UL SoM (i.MX6ULL) on OPOS6ULDev board"; + compatible = "armadeus,imx6ull-opos6uldev", "armadeus,imx6ull-opos6ul", "fsl,imx6ull"; +}; + +&iomuxc_snvs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tamper_gpios>; + + pinctrl_tamper_gpios: tampergpiosgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0b0b0 + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0 + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0 + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 + MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0b0b0 + >; + }; + + pinctrl_usbotg2_vbus: usbotg2vbusgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 + >; + }; + + pinctrl_w1: w1grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0b0b0 + >; + }; +}; |