diff options
| author | Grygorii Strashko <grygorii.strashko@ti.com> | 2019-10-07 10:59:09 -0700 |
|---|---|---|
| committer | Santosh Shilimkar <santosh.shilimkar@oracle.com> | 2019-10-07 10:59:09 -0700 |
| commit | 8cb7888d648eede1dd8d8a17db25f4062b4d00eb (patch) | |
| tree | 13ebc01d6fc3a81ce0d674073ad185b75b5dcb7e /arch/arm/boot/dts/keystone-k2hk-netcp.dtsi | |
| parent | debc91ab8fd275d003152244424ed6c224bcdf6a (diff) | |
ARM: dts: k2hk-netcp: add cpts refclk_mux node
KeyStone 66AK2H/K 1G Ethernet Switch Subsystems, can control an external
multiplexer that selects one of up to 32 clocks for time sync reference
(RFTCLK) clock. This feature can be configured through CPTS_RFTCLK_SEL
register (offset: x08) in CPTS module and modelled as multiplexer clock.
Hence, add cpts-refclk-mux clock node which allows to mux one of SYSCLK2,
SYSCLK3, TIMI0, TIMI1, TSREFCLK clocks as CPTS reference clock [1] and
group all CPTS properties under "cpts" subnode.
[1] http://www.ti.com/lit/gpn/66ak2h14
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
Diffstat (limited to 'arch/arm/boot/dts/keystone-k2hk-netcp.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/keystone-k2hk-netcp.dtsi | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi b/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi index e203145acbea..d5a6c1f5633c 100644 --- a/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi +++ b/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi @@ -152,8 +152,8 @@ netcp: netcp@2000000 { /* NetCP address range */ ranges = <0 0x2000000 0x100000>; - clocks = <&clkpa>, <&clkcpgmac>, <&chipclk12>; - clock-names = "pa_clk", "ethss_clk", "cpts"; + clocks = <&clkpa>, <&clkcpgmac>; + clock-names = "pa_clk", "ethss_clk"; dma-coherent; ti,navigator-dmas = <&dma_gbe 22>, @@ -175,6 +175,22 @@ netcp: netcp@2000000 { tx-queue = <648>; tx-channel = "nettx"; + cpts { + clocks = <&cpts_refclk_mux>; + clock-names = "cpts"; + + cpts_refclk_mux: cpts-refclk-mux { + #clock-cells = <0>; + clocks = <&chipclk12>, <&chipclk13>, + <&timi0>, <&timi1>, + <&tsrefclk>; + ti,mux-tbl = <0x0>, <0x1>, <0x2>, + <0x3>, <0x8>; + assigned-clocks = <&cpts_refclk_mux>; + assigned-clock-parents = <&chipclk12>; + }; + }; + interfaces { gbe0: interface-0 { slave-port = <0>; |