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authorVladimir Zapolskiy <vz@mleia.com>2016-07-08 01:46:41 +0300
committerOlof Johansson <olof@lixom.net>2016-10-02 22:08:11 -0700
commit8185041f5fa6f02acf75229a590e16aac028fc5e (patch)
tree703c0795e4a98dc093c171dc87f4827bcd6914fd /arch/arm/boot/dts/lpc32xx.dtsi
parent1a66b8512fae1296751386c807042889b41a486d (diff)
ARM: dts: lpc32xx: add device node for IRAM on-chip memory
The change adds a new device node with description of generic SRAM on-chip memory found on NXP LPC32xx SoC series and connected to AHB matrix slave port 3. Note that NXP LPC3220 SoC has 128KiB of SRAM memory, the other LPC3230, LPC3240 and LPC3250 SoCs all have 256KiB SRAM space, in the shared DTSI file this change specifies 128KiB SRAM size. Also it's worth to mention that the SRAM area contains of 64KiB banks, 2 banks on LPC3220 and 4 banks on the other SoCs from the series, and all SRAM banks but the first one have independent power controls, the description of this feature will be added with the introduction of power domains for the SoC series. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Cc: Sylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot/dts/lpc32xx.dtsi')
-rw-r--r--arch/arm/boot/dts/lpc32xx.dtsi12
1 files changed, 11 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index e295e1ec82a5..b5841fab51c1 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -51,9 +51,19 @@
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
- ranges = <0x20000000 0x20000000 0x30000000>,
+ ranges = <0x00000000 0x00000000 0x10000000>,
+ <0x20000000 0x20000000 0x30000000>,
<0xe0000000 0xe0000000 0x04000000>;
+ iram: sram@08000000 {
+ compatible = "mmio-sram";
+ reg = <0x08000000 0x20000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x08000000 0x20000>;
+ };
+
/*
* Enable either SLC or MLC
*/