diff options
| author | Vladimir Zapolskiy <vz@mleia.com> | 2019-04-19 23:54:46 +0300 |
|---|---|---|
| committer | Vladimir Zapolskiy <vz@mleia.com> | 2019-04-19 23:57:04 +0300 |
| commit | cea862386791e281c4e9ab07dd118321f6655435 (patch) | |
| tree | 63a94e5d0b2cf170990c97b95621c440ae1c3d03 /arch/arm/boot/dts/lpc32xx.dtsi | |
| parent | 4c546175dbe1b9bde68f547666a2c1f75d65b817 (diff) | |
ARM: dts: lpc32xx: add address and size cell values to SPI controller nodes
All 4 SPI controllers on NXP LPC32xx SoC support SPI slaves discerning them
by one cell address value, set it as default to avoid duplication in board
device tree files.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Diffstat (limited to 'arch/arm/boot/dts/lpc32xx.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/lpc32xx.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index a0fedab579b4..bc32450de423 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -187,6 +187,8 @@ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_SSP0>; clock-names = "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -194,6 +196,8 @@ compatible = "nxp,lpc3220-spi"; reg = <0x20088000 0x1000>; clocks = <&clk LPC32XX_CLK_SPI1>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -207,6 +211,8 @@ interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_SSP1>; clock-names = "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -214,6 +220,8 @@ compatible = "nxp,lpc3220-spi"; reg = <0x20090000 0x1000>; clocks = <&clk LPC32XX_CLK_SPI2>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; |