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| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2018-10-28 13:35:14 +0100 |
|---|---|---|
| committer | Kevin Hilman <khilman@baylibre.com> | 2018-11-14 17:20:11 -0800 |
| commit | be215b92703bd730fe3968ae8ee1de2e22ba5b1d (patch) | |
| tree | 58ec2bc2ede8c92dbf78c6d408cf292681f71a9b /arch/arm/boot/dts/meson6-atv1200.dts | |
| parent | e55b892e1848e220f5248583b99bdcde63fe8f05 (diff) | |
dt-bindings: timer: meson6_timer: document the clock inputs
The Meson Timer IP has two clock inputs:
- pclk which is used as "system clock" timebase of Timer E
- xtal which is used for the 1us, 10us, 100us and 1ms timebases of Timer
A, B, C, D and E
The IP block has four internal dividers (XTAL is running at 24MHz):
- "xtal div 24" for 1us resolution
- "xtal div 240" for 10us resolution
- "xtal div 2400" for 100us resolution
- "xtal div 24000" for 1ms resolution
Suggested-by: Jianxin Pan <jianxin.pan@amlogic.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'arch/arm/boot/dts/meson6-atv1200.dts')
0 files changed, 0 insertions, 0 deletions