diff options
| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2019-01-19 00:43:37 +0100 |
|---|---|---|
| committer | Kevin Hilman <khilman@baylibre.com> | 2019-02-11 12:52:26 -0800 |
| commit | b7d10841e5d7003bb8bc57c122494b4fb47836c0 (patch) | |
| tree | a43129b91e29e4294509cc8268227cbd99d4c0b8 /arch/arm/boot/dts/meson8b-ec100.dts | |
| parent | e7e871b50f80145d37d13e8fbdc73a7dd52c4d88 (diff) | |
ARM: dts: meson8b: ec100: enable the Ethernet PHY interrupt
The INTR32 pin of the IP101GR Ethernet PHY is routed to the GPIOH_3 pad
on the SoC.
Enable the interrupt function of the PHY's INTR32 pin to switch it from
it's default "receive error" mode to "interrupt pin" mode.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'arch/arm/boot/dts/meson8b-ec100.dts')
| -rw-r--r-- | arch/arm/boot/dts/meson8b-ec100.dts | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts index 0cebe849a920..74b726fc0d30 100644 --- a/arch/arm/boot/dts/meson8b-ec100.dts +++ b/arch/arm/boot/dts/meson8b-ec100.dts @@ -169,6 +169,10 @@ eth_phy0: ethernet-phy@0 { /* IC Plus IP101A/G (0x02430c54) */ reg = <0>; + icplus,select-interrupt; + interrupt-parent = <&gpio_intc>; + /* GPIOH_3 */ + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; }; }; }; |