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authorNishanth Menon <nm@ti.com>2015-05-15 17:16:40 -0500
committerTony Lindgren <tony@atomide.com>2015-05-20 11:21:24 -0700
commitba6304609879c6e342cfb8bbdc8b0dc71344c17b (patch)
tree50fee177c45733907ba77ebe39d9c93907646a23 /arch/arm/boot/dts/omap5-uevm.dts
parentf6ae941e710f4228bc13d3aefe0fbefb4012ab71 (diff)
ARM: dts: omap5-uevm: Add Uart wakeup interrupt
UART3 wakeup takes place with iodaisy chain. enable the wakeup pin. Reported-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> [tony@atomide.com: tabify uart pins properly while at it] Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/omap5-uevm.dts')
-rw-r--r--arch/arm/boot/dts/omap5-uevm.dts14
1 files changed, 8 insertions, 6 deletions
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index 74777a6e200a..275618f19a43 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -597,18 +597,20 @@
};
&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
};
&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart3_pins>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+ interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <&omap5_pmx_core 0x19c>;
};
&uart5 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart5_pins>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart5_pins>;
};
&cpu0 {