diff options
| author | Matthew McClintock <mmcclint@codeaurora.org> | 2018-07-25 10:37:45 +0200 |
|---|---|---|
| committer | Andy Gross <andy.gross@linaro.org> | 2018-09-13 15:37:36 -0500 |
| commit | 233c77d4f1d12e4337fba1146d5197f4c0f9107d (patch) | |
| tree | 591d2c168202e543df4061a617149717eeaea9cc /arch/arm/boot/dts/qcom-ipq4019.dtsi | |
| parent | bd9392507588483da81337cb430531d1cb114845 (diff) | |
ARM: dts: qcom: ipq4019: use v2 of the kpss bringup mechanism
v1 was the incorrect choice here and sometimes the board
would not come up properly.
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/qcom-ipq4019.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/qcom-ipq4019.dtsi | 25 |
1 files changed, 17 insertions, 8 deletions
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 78db67337ed4..bbb230b743b2 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -52,7 +52,8 @@ cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; - enable-method = "qcom,kpss-acc-v1"; + enable-method = "qcom,kpss-acc-v2"; + next-level-cache = <&L2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; reg = <0x0>; @@ -71,7 +72,8 @@ cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a7"; - enable-method = "qcom,kpss-acc-v1"; + enable-method = "qcom,kpss-acc-v2"; + next-level-cache = <&L2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; reg = <0x1>; @@ -90,7 +92,8 @@ cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a7"; - enable-method = "qcom,kpss-acc-v1"; + enable-method = "qcom,kpss-acc-v2"; + next-level-cache = <&L2>; qcom,acc = <&acc2>; qcom,saw = <&saw2>; reg = <0x2>; @@ -109,7 +112,8 @@ cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a7"; - enable-method = "qcom,kpss-acc-v1"; + enable-method = "qcom,kpss-acc-v2"; + next-level-cache = <&L2>; qcom,acc = <&acc3>; qcom,saw = <&saw3>; reg = <0x3>; @@ -124,6 +128,11 @@ >; clock-latency = <256000>; }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; }; pmu { @@ -292,22 +301,22 @@ }; acc0: clock-controller@b088000 { - compatible = "qcom,kpss-acc-v1"; + compatible = "qcom,kpss-acc-v2"; reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; }; acc1: clock-controller@b098000 { - compatible = "qcom,kpss-acc-v1"; + compatible = "qcom,kpss-acc-v2"; reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; }; acc2: clock-controller@b0a8000 { - compatible = "qcom,kpss-acc-v1"; + compatible = "qcom,kpss-acc-v2"; reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; }; acc3: clock-controller@b0b8000 { - compatible = "qcom,kpss-acc-v1"; + compatible = "qcom,kpss-acc-v2"; reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; }; |