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authorOlof Johansson <olof@lixom.net>2017-06-18 22:37:31 -0700
committerOlof Johansson <olof@lixom.net>2017-06-18 22:37:31 -0700
commitbf671ec65a11e87464b5bfcf4b41b0d23ec5e751 (patch)
treec37e629c92e1903a7a9b69634867409e23a023ca /arch/arm/boot/dts/qcom-ipq8064.dtsi
parent5088774b8fd052fde39ab3321b8cab2f734facd9 (diff)
parentcff94887d55a32bf8f7095482d9ba92784280a5c (diff)
Merge tag 'qcom-dts-for-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt
Qualcomm Device Tree Changes for v4.13 * Fix IPQ4019 i2c0 node * Add GSBI7 on IPQ8064 * Add misc APQ8060 devices * Fixup USB related devices on APQ8064 and MSM8974 * tag 'qcom-dts-for-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: ARM: dts: add core I2C devices to the APQ8060 Dragonboard ARM: dts: add GSBI8 defines to the MSM8660 family ARM: dts: Qualcomm APQ8060 DragonBoard ALS sensor ARM: dts: add XOADC and IIO HWMON to MSM8660/APQ8060 ARM: dts: qcom: ipq4019: fix i2c_0 node ARM: dts: qcom: add gsbi7 serial to ipq8064 SoC device tree ARM: dts: qcom-apq8064: Collapse usb support into one node ARM: dts: qcom-msm8974: Add HS usb node and OTG detection mechanisms ARM: dts: qcom: add charger otg regulator ARM: dts: qcom: Remove s4/5vs1,2 from RPM pm8941 control Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot/dts/qcom-ipq8064.dtsi')
-rw-r--r--arch/arm/boot/dts/qcom-ipq8064.dtsi23
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 76f4e8921d58..f1fbffe59b93 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -284,6 +284,29 @@
};
};
+ gsbi7: gsbi@16600000 {
+ status = "disabled";
+ compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <7>;
+ reg = <0x16600000 0x100>;
+ clocks = <&gcc GSBI7_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ syscon-tcsr = <&tcsr>;
+
+ gsbi7_serial: serial@16640000 {
+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+ reg = <0x16640000 0x1000>,
+ <0x16600000 0x1000>;
+ interrupts = <0 158 0x0>;
+ clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+ };
+
sata_phy: sata-phy@1b400000 {
compatible = "qcom,ipq806x-sata-phy";
reg = <0x1b400000 0x200>;