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| author | Arnd Bergmann <arnd@arndb.de> | 2017-10-20 00:28:13 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2017-10-20 00:38:58 +0200 |
| commit | 282e1cd16373d9b01dc64ff9f99c74d69df1812c (patch) | |
| tree | f7f49050a8f236420e967b4c95f44a5e119c1b7d /arch/arm/boot/dts/qcom-msm8660.dtsi | |
| parent | 2507514680f63f790b1567cf36704228b83dc3e6 (diff) | |
| parent | e8c4c6eeaacd0fbc18fe8954b262cfd97836a76f (diff) | |
Merge tag 'qcom-dts-for-4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/soc
Pull "Qualcomm Device Tree Changes for v4.15" from Andy Gross:
* Add Support for MSM8974 based Fairphone 2 phone
* Add support for MSM8974 based Sony Xperia Z2 Tablet
* Add MSM8660 GSBI6/7 nodes
* Disable GSBI6 at APQ8064 platform level
* Fix phy cells on APQ8064
* tag 'qcom-dts-for-4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
ARM: dts: msm8974-FP2: Add USB node
ARM: dts: msm8974-FP2: Add sdhci1 node
ARM: dts: msm8974-FP2: Add regulator nodes for FP2
ARM: dts: msm8974-FP2: Introduce gpio-keys nodes
ARM: dts: qcom: Add initial DTS file for Fairphone 2 phone
ARM: dts: qcom: add MSM8660 GSBI6 and GSBI7
ARM: dts: qcom: msm8974: Add Sony Xperia Z2 Tablet
ARM: dts: qcom-apq8064: disable gsbi6 i2c by default at soc dtsi
ARM: dts: qcom-apq8064: Fix dsi and hdmi phy cells
Diffstat (limited to 'arch/arm/boot/dts/qcom-msm8660.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/qcom-msm8660.dtsi | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index a5fef54f4718..f2c01c670cbe 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -123,6 +123,73 @@ reg = <0x900000 0x4000>; }; + gsbi6: gsbi@16500000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <12>; + reg = <0x16500000 0x100>; + clocks = <&gcc GSBI6_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + gsbi6_serial: serial@16540000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16540000 0x1000>, + <0x16500000 0x1000>; + interrupts = <GIC_SPI 156 IRQ_TYPE_NONE>; + clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + gsbi6_i2c: i2c@16580000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16580000 0x1000>; + interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>; + clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + gsbi7: gsbi@16600000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <12>; + reg = <0x16600000 0x100>; + clocks = <&gcc GSBI7_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + gsbi7_serial: serial@16640000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16640000 0x1000>, + <0x16600000 0x1000>; + interrupts = <GIC_SPI 158 IRQ_TYPE_NONE>; + clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + gsbi7_i2c: i2c@16680000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16680000 0x1000>; + interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>; + clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; gsbi8: gsbi@19800000 { compatible = "qcom,gsbi-v1.0.0"; |