diff options
| author | Rohit Agarwal <quic_rohiagar@quicinc.com> | 2022-02-22 10:26:23 +0530 |
|---|---|---|
| committer | Bjorn Andersson <bjorn.andersson@linaro.org> | 2022-04-12 21:22:26 -0500 |
| commit | 02c5553523c6cfdab4335ab26ff65f679c7c91ac (patch) | |
| tree | f9bee50becb3c19c8ddf555fa729a1fe83dda8f3 /arch/arm/boot/dts/qcom-sdx65.dtsi | |
| parent | c20aa951ee14fe0dfa2beed19aaee1fd33d50a6e (diff) | |
ARM: dts: qcom: sdx65: Add support for A7 PLL clock
On SDX65 there is a separate A7 PLL which is used to provide high
frequency clock to the Cortex A7 CPU via a MUX.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1645505785-2271-4-git-send-email-quic_rohiagar@quicinc.com
Diffstat (limited to 'arch/arm/boot/dts/qcom-sdx65.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/qcom-sdx65.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 796641d30e06..6b3a502c0ce2 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -121,6 +121,14 @@ <0x17802000 0x1000>; }; + a7pll: clock@17808000 { + compatible = "qcom,sdx55-a7pll"; + reg = <0x17808000 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <0>; + }; + timer@17820000 { #address-cells = <1>; #size-cells = <1>; |