diff options
| author | Rohit Agarwal <quic_rohiagar@quicinc.com> | 2022-02-22 10:26:24 +0530 |
|---|---|---|
| committer | Bjorn Andersson <bjorn.andersson@linaro.org> | 2022-04-12 21:22:34 -0500 |
| commit | ce91bc005e076acd3415d557d7e7c488aa9ab10d (patch) | |
| tree | d4570585c3f044182e0e9792f7f91bd926d503bf /arch/arm/boot/dts/qcom-sdx65.dtsi | |
| parent | 02c5553523c6cfdab4335ab26ff65f679c7c91ac (diff) | |
ARM: dts: qcom: sdx65: Add support for APCS block
The APCS block on SDX65 acts as a mailbox controller and also provides
clock output for the Cortex A7 CPU.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1645505785-2271-5-git-send-email-quic_rohiagar@quicinc.com
Diffstat (limited to 'arch/arm/boot/dts/qcom-sdx65.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/qcom-sdx65.dtsi | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 6b3a502c0ce2..14579121be5a 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -129,6 +129,15 @@ #clock-cells = <0>; }; + apcs: mailbox@17810000 { + compatible = "qcom,sdx55-apcs-gcc", "syscon"; + reg = <0x17810000 0x2000>; + #mbox-cells = <1>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>; + clock-names = "ref", "pll", "aux"; + #clock-cells = <0>; + }; + timer@17820000 { #address-cells = <1>; #size-cells = <1>; |