diff options
| author | Chris Brandt <chris.brandt@renesas.com> | 2019-04-30 08:23:07 -0500 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2019-05-20 13:16:55 +0200 |
| commit | a49f76cddaee89ffe7e72cf6e38c3635b97058b8 (patch) | |
| tree | 978641f45c4f50c80dbb38e3de1d375b0745cc30 /arch/arm/boot/dts/r7s9210.dtsi | |
| parent | 49da03c67c36134363b9fee558e86d39db8147d4 (diff) | |
ARM: dts: r7s9210: Add SDHI support
Add SDHI support for the R7S9210 (RZ/A2) SoC.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r7s9210.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r7s9210.dtsi | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi index 1cd982c9920f..2eaa5eeba509 100644 --- a/arch/arm/boot/dts/r7s9210.dtsi +++ b/arch/arm/boot/dts/r7s9210.dtsi @@ -322,6 +322,30 @@ status = "disabled"; }; + sdhi0: sd@e8228000 { + compatible = "renesas,sdhi-r7s9210"; + reg = <0xe8228000 0x8c0>; + interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 103>, <&cpg CPG_MOD 102>; + clock-names = "core", "cd"; + power-domains = <&cpg>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + sdhi1: sd@e822a000 { + compatible = "renesas,sdhi-r7s9210"; + reg = <0xe822a000 0x8c0>; + interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 101>, <&cpg CPG_MOD 100>; + clock-names = "core", "cd"; + power-domains = <&cpg>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + gic: interrupt-controller@e8221000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; |