diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2016-05-20 09:09:54 +0200 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2016-05-30 09:37:09 +0900 |
| commit | 28c8c0aa095360ec14c3bcbe7f3ed378faf1daac (patch) | |
| tree | 1cd0bbe0ddb5d13447177e852adba901bef485d1 /arch/arm/boot/dts/r8a7740.dtsi | |
| parent | b0da45c60d2f7b08128a6cd1216ac0ac7d8954c7 (diff) | |
ARM: dts: r8a7740: Fix W=1 dtc warnings
Warning (unit_address_vs_reg): Node /cache-controller has a reg or ranges property, but no unit name
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7740.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7740.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 39b2f88ad151..159e04eb1b9e 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -39,7 +39,7 @@ <0xc2000000 0x1000>; }; - L2: cache-controller { + L2: cache-controller@f0100000 { compatible = "arm,pl310-cache"; reg = <0xf0100000 0x1000>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |