diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2020-02-18 14:30:17 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2020-02-24 14:03:33 +0100 |
| commit | 9e1232631d4e8e30096fa758a0e1fb9e08f219f9 (patch) | |
| tree | e6230c694a57a61f6e2af602c738bc9be1f03c87 /arch/arm/boot/dts/r8a7743.dtsi | |
| parent | d15881f29ee8d6fada59597741d1a944de117df7 (diff) | |
ARM: dts: rzg1: Add reset control properties for display
Add reset control properties to the devices node for the Display Units
on all supported RZ/G1 SoCs. Note that on these SoCs, there is only a
single reset for all DU channels.
Join the clocks lines while at it, to increase uniformity.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20200218133019.22299-3-geert+renesas@glider.be
Diffstat (limited to 'arch/arm/boot/dts/r8a7743.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7743.dtsi | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 1cd19a569bd0..e8b340bb99bc 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -1669,9 +1669,10 @@ reg = <0 0xfeb00000 0 0x40000>; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; clock-names = "du.0", "du.1"; + resets = <&cpg 724>; + reset-names = "du.0"; status = "disabled"; ports { |