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authorGeert Uytterhoeven <geert+renesas@glider.be>2017-10-12 11:35:09 +0200
committerSimon Horman <horms+renesas@verge.net.au>2017-10-16 11:38:21 +0200
commitfa9f95a3d1bf827e7b83310e5e5c83f36382e25f (patch)
tree1082d07a6836b428bcdde442d02eb9b7cfd155c3 /arch/arm/boot/dts/r8a7779.dtsi
parentd3e865a35a4f8cee0d0b86d7cd6d05908f01a874 (diff)
ARM: dts: r8a7779: Add clocks for CA9 CPU cores
Improve hardware description by adding clocks properties to the device nodes corresponding to the CA9 CPU cores. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7779.dtsi')
-rw-r--r--arch/arm/boot/dts/r8a7779.dtsi4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index ccef2cfab6e0..e8eb94748b27 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -29,12 +29,14 @@
compatible = "arm,cortex-a9";
reg = <0>;
clock-frequency = <1000000000>;
+ clocks = <&cpg_clocks R8A7779_CLK_Z>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
clock-frequency = <1000000000>;
+ clocks = <&cpg_clocks R8A7779_CLK_Z>;
power-domains = <&sysc R8A7779_PD_ARM1>;
};
cpu@2 {
@@ -42,6 +44,7 @@
compatible = "arm,cortex-a9";
reg = <2>;
clock-frequency = <1000000000>;
+ clocks = <&cpg_clocks R8A7779_CLK_Z>;
power-domains = <&sysc R8A7779_PD_ARM2>;
};
cpu@3 {
@@ -49,6 +52,7 @@
compatible = "arm,cortex-a9";
reg = <3>;
clock-frequency = <1000000000>;
+ clocks = <&cpg_clocks R8A7779_CLK_Z>;
power-domains = <&sysc R8A7779_PD_ARM3>;
};
};