diff options
| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2016-06-17 01:02:48 +0300 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2016-06-24 11:04:35 +0900 |
| commit | eebc8e2c5b7a3db19075a02730db8b73be933485 (patch) | |
| tree | 2d7d669d90344b76e320f9b1489338b1a3207441 /arch/arm/boot/dts/r8a7792.dtsi | |
| parent | adc47ecf5a8d35f8060c88ac818cd5404268f3ed (diff) | |
ARM: dts: r8a7792: add JPU clocks
Add JPU clock and its parent, M2 clock to the R8A7792 device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7792.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7792.dtsi | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 18b4e50521c3..7077c5db2678 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -280,8 +280,24 @@ clock-div = <48>; clock-mult = <1>; }; + m2_clk: m2 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7792_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + }; /* Gate clocks */ + mstp1_clks: mstp1_clks@e6150134 { + compatible = "renesas,r8a7792-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; + clocks = <&m2_clk>; + #clock-cells = <1>; + clock-indices = <R8A7792_CLK_JPU>; + clock-output-names = "jpu"; + }; mstp2_clks: mstp2_clks@e6150138 { compatible = "renesas,r8a7792-mstp-clocks", "renesas,cpg-mstp-clocks"; |