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authorSergei Shtylyov <sergei.shtylyov@cogentembedded.com>2016-08-05 21:26:25 +0300
committerSimon Horman <horms+renesas@verge.net.au>2016-08-09 14:37:47 +0200
commit8bec0842ba2bb1b3bd954a1ef50f426b8f09c84f (patch)
treecaf4c14d14fa274b618aa8873a07d861f5458e4e /arch/arm/boot/dts/r8a7792.dtsi
parent3b0211af06298682d5faaa4c4cedf666fb1281c3 (diff)
ARM: dts: r8a7792: add DU support
Define the generic R8A7792 part of the DU device node. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7792.dtsi')
-rw-r--r--arch/arm/boot/dts/r8a7792.dtsi28
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 7e0c57ff9892..9763289db5ce 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -556,6 +556,34 @@
status = "disabled";
};
+ du: display@feb00000 {
+ compatible = "renesas,du-r8a7792";
+ reg = <0 0xfeb00000 0 0x40000>;
+ reg-names = "du";
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7792_CLK_DU0>,
+ <&mstp7_clks R8A7792_CLK_DU1>;
+ clock-names = "du.0", "du.1";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_rgb0: endpoint {
+ };
+ };
+ port@1 {
+ reg = <1>;
+ du_out_rgb1: endpoint {
+ };
+ };
+ };
+ };
+
can0: can@e6e80000 {
compatible = "renesas,can-r8a7792",
"renesas,rcar-gen2-can";