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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2015-06-02 14:33:46 +0200 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2016-02-19 14:52:22 +0900 |
| commit | 8ffe93a5b2cb55d4da9c285d9277699bdb828b47 (patch) | |
| tree | 873ad3e0e94e30f402c550fe694fa41b6f22e407 /arch/arm/boot/dts/r8a7793.dtsi | |
| parent | fb1cecd40690e61e122d7249e7499c8d799feffb (diff) | |
ARM: dts: r8a7791: Add L2 cache-controller node
Add a device node for the L2 cache, and link the CPU nodes to it.
The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7793.dtsi')
0 files changed, 0 insertions, 0 deletions