diff options
| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2015-08-20 01:00:09 +0300 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2015-09-14 10:16:38 +0900 |
| commit | 5428521ba123dddda4d2ac9ab19d173b692a8acb (patch) | |
| tree | 887c3da31edd20ea2d7570ec3afcecd4a66745a4 /arch/arm/boot/dts/r8a7794.dtsi | |
| parent | 755252d0e502627df6ddabbb2d628705bc256497 (diff) | |
ARM: shmobile: r8a7794: add I2C DT support
Define the generic R8A7794 parts of the I2C[0-5] device nodes.
Based on the original patch by Koji Matsuoka <koji.matsuoka.xm@renesas.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7794.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7794.dtsi | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index e0f32ede2181..7384db2a3992 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -20,6 +20,12 @@ #size-cells = <2>; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; spi0 = &qspi; }; @@ -502,6 +508,73 @@ status = "disabled"; }; + /* The memory map in the User's Manual maps the cores to bus numbers */ + i2c0: i2c@e6508000 { + compatible = "renesas,i2c-r8a7794"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7794_CLK_I2C0>; + power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@e6518000 { + compatible = "renesas,i2c-r8a7794"; + reg = <0 0xe6518000 0 0x40>; + interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7794_CLK_I2C1>; + power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@e6530000 { + compatible = "renesas,i2c-r8a7794"; + reg = <0 0xe6530000 0 0x40>; + interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7794_CLK_I2C2>; + power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@e6540000 { + compatible = "renesas,i2c-r8a7794"; + reg = <0 0xe6540000 0 0x40>; + interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7794_CLK_I2C3>; + power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@e6520000 { + compatible = "renesas,i2c-r8a7794"; + reg = <0 0xe6520000 0 0x40>; + interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7794_CLK_I2C4>; + power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@e6528000 { + compatible = "renesas,i2c-r8a7794"; + reg = <0 0xe6528000 0 0x40>; + interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7794_CLK_I2C5>; + power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + mmcif0: mmc@ee200000 { compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; |