diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-05-19 14:31:37 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-05-25 10:02:59 +0200 |
| commit | a499e40a397c17a40af8a5f8ef408fe63be4c257 (patch) | |
| tree | 994f16a03fc734242a9a18b5bf0781d9fc3caa6b /arch/arm/boot/dts/r8a7794.dtsi | |
| parent | ebc666f39ff67a01e748c34d670ddf05a9e45220 (diff) | |
ARM: dts: renesas: Move enable-method to CPU nodes
According to Documentation/devicetree/bindings/arm/cpus.yaml, the
"enable-method" property should be a property of the individual CPU
nodes, and not of the parent "cpus" container node.
However, on R-Car Gen2 and RZ/G1 SoCs, the property is tied to the
"cpus" node instead.
Secondary CPU bringup and CPU hot (un)plug work regardless, as
arm_dt_init_cpu_maps() falls back to looking in the "cpus" node.
The cpuidle code does not have such a fallback, so it does not detect
the enable-method. Note that cpuidle does not support the
"renesas,apmu" enable-method yet, so for now this does not make any
difference.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/35fcfedf9de9269185c48ca5a6dfcba7cdd3484b.1621427319.git.geert+renesas@glider.be
Diffstat (limited to 'arch/arm/boot/dts/r8a7794.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7794.dtsi | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 0035770e74de..eac9ed8df0be 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -62,7 +62,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -71,6 +70,7 @@ clock-frequency = <1000000000>; clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; power-domains = <&sysc R8A7794_PD_CA7_CPU0>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA7>; }; @@ -81,6 +81,7 @@ clock-frequency = <1000000000>; clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; power-domains = <&sysc R8A7794_PD_CA7_CPU1>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA7>; }; |