diff options
| author | Michel Pollet <michel.pollet@bp.renesas.com> | 2018-06-28 09:17:14 +0100 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2018-07-23 13:33:05 +0200 |
| commit | f8fc94dbcf2d166b865991afb6c827aa56dc0de2 (patch) | |
| tree | dc39ef93572f4fc97f09e9c731d7cce9dd51f810 /arch/arm/boot/dts/r9a06g032.dtsi | |
| parent | df7112c9461458c2a2069e9a4a7962fd16bf62bf (diff) | |
ARM: dts: Renesas R9A06G032 SMP enable method
Add a special enable method for the second CA7 of the R9A06G032
as well as the default value for the "cpu-release-addr" property.
Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r9a06g032.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r9a06g032.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 339d0958011e..afe29c95a006 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -29,6 +29,8 @@ compatible = "arm,cortex-a7"; reg = <1>; clocks = <&sysctrl 84>; + enable-method = "renesas,r9a06g032-smp"; + cpu-release-addr = <0 0x4000c204>; }; }; |