diff options
| author | Elaine Zhang <zhangqing@rock-chips.com> | 2017-05-17 18:16:14 +0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2017-05-19 13:17:22 +0200 |
| commit | 30ee58146b53d83e90fc5326488e1e48a5a3aba4 (patch) | |
| tree | f1cc2ddb3edcd306859146f6f7150a05fedb9ce0 /arch/arm/boot/dts/rk322x.dtsi | |
| parent | 738e451174d428881910b9b7558965668216ed5b (diff) | |
ARM: dts: rockchip: set default rates for core clocks on rk322x
Set sane default frequencies for CPLL, GPLL and some other core clocks
on the rk322x.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/boot/dts/rk322x.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/rk322x.dtsi | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 816b0796d816..c256df9a2cd8 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -346,8 +346,18 @@ rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>; - assigned-clock-rates = <594000000>; + assigned-clocks = + <&cru PLL_GPLL>, <&cru ARMCLK>, + <&cru PLL_CPLL>, <&cru ACLK_PERI>, + <&cru HCLK_PERI>, <&cru PCLK_PERI>, + <&cru ACLK_CPU>, <&cru HCLK_CPU>, + <&cru PCLK_CPU>; + assigned-clock-rates = + <594000000>, <816000000>, + <500000000>, <150000000>, + <150000000>, <75000000>, + <150000000>, <150000000>, + <75000000>; }; thermal-zones { |