diff options
| author | Matthias Kaehlcke <mka@chromium.org> | 2020-01-06 13:52:13 -0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2020-01-07 22:52:40 +0100 |
| commit | 1f5e928340061bc9729c82591ec4379909e708d6 (patch) | |
| tree | 6987dd86f345bc7110d0703f429ae9f18c0c2bba /arch/arm/boot/dts/rk3288-veyron-fievel.dts | |
| parent | e964d463392d70d801c15f83d02e61671f35d549 (diff) | |
ARM: dts: rockchip: Use ABI name for write protect pin on veyron fievel/tiger
The flash write protect pin is currently named 'FW_WP_AP', which is
how the signal is called in the schematics. The Chrome OS ABI
requires the pin to be named 'AP_FLASH_WP_L', which is also how
it is called on all other veyron devices. Rename the pin to match
the ABI.
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20200106135142.1.I3f99ac8399a564c88ff48ae6290cc691b47c16ae@changeid
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/boot/dts/rk3288-veyron-fievel.dts')
| -rw-r--r-- | arch/arm/boot/dts/rk3288-veyron-fievel.dts | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/rk3288-veyron-fievel.dts b/arch/arm/boot/dts/rk3288-veyron-fievel.dts index 7e7ef8e06b8d..6ece7141ddbe 100644 --- a/arch/arm/boot/dts/rk3288-veyron-fievel.dts +++ b/arch/arm/boot/dts/rk3288-veyron-fievel.dts @@ -380,7 +380,11 @@ "PWR_LED1", "TPM_INT_H", "SPK_ON", - "FW_WP_AP", + /* + * AP_FLASH_WP_L is Chrome OS ABI. Schematics call + * it FW_WP_AP. + */ + "AP_FLASH_WP_L", "", "CPU_NMI", |