diff options
| author | Linus Walleij <linus.walleij@linaro.org> | 2013-10-18 09:49:21 +0200 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2013-10-18 13:25:46 +0200 |
| commit | d591640adc7beaf816c2ffc0952d25b836cb3fcf (patch) | |
| tree | da284560aa1dcfbd8bfca58303b5306b63cbc2dd /arch/arm/boot/dts/ste-dbx5x0.dtsi | |
| parent | f5ff9a115ec633852312a8e43df4bbd36b4dad3d (diff) | |
ARM: ux500: fix clock for GPIO blocks 6 and 7
The clock assignment in the device tree for GPIO blocks 6
and 7 was incorrect, indicating this was managed by bit 1 on
PRCC 2 while it was in fact bit 11 on PRCC 2.
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/ste-dbx5x0.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/ste-dbx5x0.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 55abf1292ddd..5112f4cd8bce 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -197,7 +197,7 @@ #gpio-cells = <2>; gpio-bank = <6>; - clocks = <&prcc_pclk 2 1>; + clocks = <&prcc_pclk 2 11>; }; gpio7: gpio@8011e080 { @@ -212,7 +212,7 @@ #gpio-cells = <2>; gpio-bank = <7>; - clocks = <&prcc_pclk 2 1>; + clocks = <&prcc_pclk 2 11>; }; gpio8: gpio@a03fe000 { |