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| author | Alexandre Torgue <alexandre.torgue@st.com> | 2019-11-19 10:06:57 +0100 |
|---|---|---|
| committer | Alexandre Torgue <alexandre.torgue@st.com> | 2019-12-09 09:19:15 +0100 |
| commit | 95e395c881b35101578f8a7e1041cebcf21d7d79 (patch) | |
| tree | 5602d609e4a20f6b4a176b241eac4a231fa944c5 /arch/arm/boot/dts/stm32mp153.dtsi | |
| parent | 48c7181fa79fbaf6019087a590092b014bc567aa (diff) | |
ARM: dts: stm32: Introduce new STM32MP15 SOCs: STM32MP151 and STM32MP153
STM32MP151 and STM32MP153 were not explicitly supported through
stm32mp157c.dts. This commit adds dedicated files to support all STM32MP15
SOCs family.
The differences between those SOCs are:
-STM32MP151 [1]: common file.
-STM32MP153 [2]: STM32MP151 + CANs + a second CortexA7-CPU.
-STM32MP157 [3]: STM32MP153 + DSI + GPU.
[1] https://www.st.com/resource/en/reference_manual/dm00366349.pdf
[2] https://www.st.com/resource/en/reference_manual/dm00366355.pdf
[3] https://www.st.com/resource/en/reference_manual/dm00327659.pdf
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Diffstat (limited to 'arch/arm/boot/dts/stm32mp153.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/stm32mp153.dtsi | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/stm32mp153.dtsi b/arch/arm/boot/dts/stm32mp153.dtsi new file mode 100644 index 000000000000..2d759fc6015c --- /dev/null +++ b/arch/arm/boot/dts/stm32mp153.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. + */ + +#include "stm32mp151.dtsi" + +/ { + cpus { + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + }; + + soc { + m_can1: can@4400e000 { + compatible = "bosch,m_can"; + reg = <0x4400e000 0x400>, <0x44011000 0x1400>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; + status = "disabled"; + }; + + m_can2: can@4400f000 { + compatible = "bosch,m_can"; + reg = <0x4400f000 0x400>, <0x44011000 0x2800>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; + status = "disabled"; + }; + }; +}; |