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authorBich HEMON <bich.hemon@st.com>2018-11-15 08:52:29 +0000
committerAlexandre Torgue <alexandre.torgue@st.com>2018-12-03 09:56:20 +0100
commitd44d6e021301b6a8d95bf6a92e8aae640de2770a (patch)
treea09bc1e13a42fefde4bdd517889933ad78d55f9e /arch/arm/boot/dts/stm32mp157c.dtsi
parent5ae71cea1aec476a115dcf931807548cd26160ec (diff)
ARM: dts: stm32: change CAN RAM mapping on stm32mp157c
Split the 10Kbytes CAN message RAM to be able to use simultaneously FDCAN1 and FDCAN2 instances. First 5Kbytes are allocated to FDCAN1 and last 5Kbytes are used for FDCAN2. To do so, set the offset to 0x1400 in mram-cfg for FDCAN2. Signed-off-by: Bich Hemon <bich.hemon@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Diffstat (limited to 'arch/arm/boot/dts/stm32mp157c.dtsi')
-rw-r--r--arch/arm/boot/dts/stm32mp157c.dtsi4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi
index 2e9df63f9997..b0961cccfd14 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -742,14 +742,14 @@
m_can1: can@4400e000 {
compatible = "bosch,m_can";
- reg = <0x4400e000 0x400>, <0x44011000 0x2800>;
+ reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
reg-names = "m_can", "message_ram";
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
- bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
+ bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
status = "disabled";
};