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| author | Maxime Ripard <maxime.ripard@free-electrons.com> | 2016-06-22 11:15:55 +0200 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2016-07-04 21:18:11 +0200 |
| commit | 73ba3a1c64a4c5a1a4b87c773714814eecb84877 (patch) | |
| tree | bceada543b22eaf161c181500c1f1eb418489daf /arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts | |
| parent | 6a706356b4456204fd89ef3fbfc6ed4165cebf37 (diff) | |
ARM: sun5i: Allow PLL3 2x fixed factor clock to change PLL3 rate
In order to be able to properly generate its pixel clock, the pll3-2x fixed
factor needs to be able to change the PLL3 rate too.
Add the needed extra compatible so that it behaves that way.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts')
0 files changed, 0 insertions, 0 deletions