diff options
| author | Maxime Ripard <maxime.ripard@bootlin.com> | 2018-11-22 11:18:09 +0100 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2018-11-28 15:14:13 +0100 |
| commit | bb4d3ec9a7daa327608e69bb45704f76e2d9413c (patch) | |
| tree | e8309506c77591b0b2bb8051f3155437123517db /arch/arm/boot/dts/sun7i-a20.dtsi | |
| parent | 85a8c520ca41c719d552595d0aac456ac84b8a33 (diff) | |
ARM: dts: sun7i: Split the RTS and CTS pins out of the UART nodes
Some UART nodes on the A20 DTSI do not share the same pattern that we use
everywhere else, with the RTS and CTS pins split away from the TX and RX
pins. Make those pin groups consistent with the rest of our DT.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'arch/arm/boot/dts/sun7i-a20.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/sun7i-a20.dtsi | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 75669fc51de5..bffd3a21bee3 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -935,12 +935,22 @@ }; uart2_pi_pins: uart2-pi-pins { - pins = "PI16", "PI17", "PI18", "PI19"; + pins = "PI18", "PI19"; + function = "uart2"; + }; + + uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins { + pins = "PI16", "PI17"; function = "uart2"; }; uart3_pg_pins: uart3-pg-pins { - pins = "PG6", "PG7", "PG8", "PG9"; + pins = "PG6", "PG7"; + function = "uart3"; + }; + + uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins { + pins = "PG8", "PG9"; function = "uart3"; }; |