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authorHans de Goede <hdegoede@redhat.com>2015-06-02 15:37:32 +0200
committerMaxime Ripard <maxime.ripard@free-electrons.com>2015-07-06 13:35:47 +0200
commit4f8449b1baed5c4f6c577f1f5ef6918886583fc5 (patch)
treef66b4428b3d9b749b7a3b08a6d326f461718e69c /arch/arm/boot/dts/sun8i-a33.dtsi
parent5c4f81c1b436ade8dfcec82a47a15310c9456415 (diff)
ARM: dts: sun8i: Add A33 usb-phy and otg nodes
Note these are added to the sun8i-a33.dtsi file rather then to the shared sun8i-a23-a33.dtsi file as both the phy and the otg controller on the a33 are slightly different. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun8i-a33.dtsi')
-rw-r--r--arch/arm/boot/dts/sun8i-a33.dtsi33
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
index 85ee08098b7b..faa7d3c1fcea 100644
--- a/arch/arm/boot/dts/sun8i-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -80,6 +80,39 @@
clock-output-names = "mbus";
};
};
+
+ soc@01c00000 {
+ usb_otg: usb@01c19000 {
+ compatible = "allwinner,sun8i-a33-musb";
+ reg = <0x01c19000 0x0400>;
+ clocks = <&ahb1_gates 24>;
+ resets = <&ahb1_rst 24>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mc";
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ extcon = <&usbphy 0>;
+ status = "disabled";
+ };
+
+ usbphy: phy@01c19400 {
+ compatible = "allwinner,sun8i-a33-usb-phy";
+ reg = <0x01c19400 0x14>,
+ <0x01c1a800 0x4>;
+ reg-names = "phy_ctrl",
+ "pmu1";
+ clocks = <&usb_clk 8>,
+ <&usb_clk 9>;
+ clock-names = "usb0_phy",
+ "usb1_phy";
+ resets = <&usb_clk 0>,
+ <&usb_clk 1>;
+ reset-names = "usb0_reset",
+ "usb1_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+ };
};
&pio {