diff options
| author | Jernej Skrabec <jernej.skrabec@gmail.com> | 2021-11-20 08:34:48 +0100 |
|---|---|---|
| committer | Maxime Ripard <maxime@cerno.tech> | 2021-11-22 10:03:33 +0100 |
| commit | 38df5750962c61b96d4e53358f31955fe310d4f5 (patch) | |
| tree | 9d9314dc7d18b0c55d59b8bbb0913d79823f3552 /arch/arm/boot/dts/sunxi-h3-h5.dtsi | |
| parent | 3047444def125d9e1fb788541e8dc18a7058a47a (diff) | |
ARM: dts: sunxi: Add CEC clock to DW-HDMI
Experimentation determined that HDMI CEC controller inside DW HDMI block
depends on 32k clock from RTC. If this clock is tampered with, HDMI CEC
communication starts or stops working, depending on situation.
SoC user manual doesn't say anything about CEC, so this was overlooked.
Fix this by adding dependency to RTC 32k clock.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20211120073448.32480-3-jernej.skrabec@gmail.com
Diffstat (limited to 'arch/arm/boot/dts/sunxi-h3-h5.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/sunxi-h3-h5.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index c7428df9469e..d1e974886fdf 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -813,8 +813,8 @@ reg-io-width = <1>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, - <&ccu CLK_HDMI>; - clock-names = "iahb", "isfr", "tmds"; + <&ccu CLK_HDMI>, <&rtc 0>; + clock-names = "iahb", "isfr", "tmds", "cec"; resets = <&ccu RST_BUS_HDMI1>; reset-names = "ctrl"; phys = <&hdmi_phy>; |