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authorHans Verkuil <hans.verkuil@cisco.com>2017-09-11 14:29:50 +0200
committerThierry Reding <treding@nvidia.com>2017-10-19 11:45:14 +0200
commit7f2b7ceeb40972030a426b7cb22115b4c82281cd (patch)
treeba1cb5715d5b0316ddec0d621183bec5f8175ac9 /arch/arm/boot/dts/tegra124.dtsi
parent2bd6bf03f4c1c59381d62c61d03f6cc3fe71f66e (diff)
ARM: tegra: Add CEC support for Tegra124
Add support for the Tegra CEC IP to the Tegra124 DTSI and link it to the HDMI controller via phandle. Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra124.dtsi')
-rw-r--r--arch/arm/boot/dts/tegra124.dtsi12
1 files changed, 11 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 8baf00b89efb..87d4bdcdd362 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -124,7 +124,7 @@
nvidia,head = <1>;
};
- hdmi@54280000 {
+ hdmi: hdmi@54280000 {
compatible = "nvidia,tegra124-hdmi";
reg = <0x0 0x54280000 0x0 0x00040000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
@@ -852,6 +852,16 @@
status = "disabled";
};
+ cec@70015000 {
+ compatible = "nvidia,tegra124-cec";
+ reg = <0x0 0x70015000 0x0 0x00001000>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA124_CLK_CEC>;
+ clock-names = "cec";
+ status = "disabled";
+ hdmi-phandle = <&hdmi>;
+ };
+
soctherm: thermal-sensor@700e2000 {
compatible = "nvidia,tegra124-soctherm";
reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */