diff options
| author | Thierry Reding <treding@nvidia.com> | 2020-11-20 21:27:12 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2020-11-26 19:06:47 +0100 |
| commit | 6fb123f1f5a42136161b7782d9635a684f3036d2 (patch) | |
| tree | 76be9e7d56593cf13286b78ee90ea5d1d6f752a4 /arch/arm/boot/dts/tegra124.dtsi | |
| parent | 17401ce98ec6105db8e351c12735b6cc20d73d7e (diff) | |
ARM: tegra: Properly align clocks for SOCTHERM
Entries on subsequent lines should be aligned with the entry on the
first line.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra124.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/tegra124.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 27fb6a49118f..d7001b27c3e6 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -902,7 +902,7 @@ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "thermal", "edp"; clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, - <&tegra_car TEGRA124_CLK_SOC_THERM>; + <&tegra_car TEGRA124_CLK_SOC_THERM>; clock-names = "tsensor", "soctherm"; resets = <&tegra_car 78>; reset-names = "soctherm"; |