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authorOlof Johansson <olof@lixom.net>2019-12-05 13:16:58 -0800
committerOlof Johansson <olof@lixom.net>2019-12-05 13:18:54 -0800
commit942e6f8a8314e5550e254519dfba4ccd5170421d (patch)
tree75ec655b440fbc1c454247af38b5596dd8c78de9 /arch/arm/boot/dts/tegra20-trimslice.dts
parent336bab731be76a90291697e51d2aed0ad67d7cb5 (diff)
parentb08baef02b26cf7c2123e4a24a2fa1fb7a593ffb (diff)
Merge mainline/master into arm/fixes
This brings in the mainline tree right after armsoc contents was merged this release cycle, so that we can re-run savedefconfig, etc. Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot/dts/tegra20-trimslice.dts')
-rw-r--r--arch/arm/boot/dts/tegra20-trimslice.dts11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 3e5ac096d85e..8debd3d3c20d 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -3,6 +3,7 @@
#include <dt-bindings/input/input.h>
#include "tegra20.dtsi"
+#include "tegra20-cpu-opp.dtsi"
/ {
model = "Compulab TrimSlice board";
@@ -471,4 +472,14 @@
<&tegra_car TEGRA20_CLK_CDEV1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
+
+ cpus {
+ cpu0: cpu@0 {
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu@1 {
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ };
};