diff options
| author | Philippe Schenker <philippe.schenker@toradex.com> | 2019-08-14 10:53:38 +0000 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-10-29 20:29:14 +0100 |
| commit | 05a6a629f0e104aca6371d81dbe6ad56b0cea188 (patch) | |
| tree | 0e70d9c260c5fb0a0b143186ff0642868ca21510 /arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi | |
| parent | f0dbca55adb9daae1bcc7cb84f4d046ef44370c2 (diff) | |
ARM: tegra: Add stmpe-adc DT node to Toradex T30 modules
Add the stmpe-adc DT node as found on Toradex T30 modules
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi index 02f8126481a2..8b7a827d604d 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi @@ -994,11 +994,17 @@ id = <0>; blocks = <0x5>; irq-trigger = <0x1>; + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; stmpe_touchscreen { compatible = "st,stmpe-ts"; - /* 3.25 MHz ADC clock speed */ - st,adc-freq = <1>; /* 8 sample average control */ st,ave-ctrl = <3>; /* 7 length fractional part in z */ @@ -1008,17 +1014,17 @@ * current limit value */ st,i-drive = <1>; - /* 12-bit ADC */ - st,mod-12b = <1>; - /* internal ADC reference */ - st,ref-sel = <0>; - /* ADC converstion time: 80 clocks */ - st,sample-time = <4>; /* 1 ms panel driver settling time */ st,settling = <3>; /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; }; + + stmpe_adc { + compatible = "st,stmpe-adc"; + /* forbid to use ADC channels 3-0 (touch) */ + st,norequest-mask = <0x0F>; + }; }; /* |