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authorMichael Walle <michael@walle.cc>2021-06-16 17:54:37 +0200
committerMichal Simek <michal.simek@xilinx.com>2021-08-06 12:22:40 +0200
commitc387eea58f931fe5d008df88cc75dfc3c704e3bf (patch)
tree5ff6e26f7ecdb258bed2b7c9b3205afaab714283 /arch/arm/boot/dts/zynq-ebaz4205.dts
parent3bf9899f87d8709f55138ccbec30b3339b42be56 (diff)
ARM: dts: ebaz4205: enable NAND support
The board features a 128MiB NAND chip and recently linux gained support for the NAND controller on the Zynq SoC. Thus add the corresponding devicetree nodes. Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20210616155437.27378-4-michael@walle.cc Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/boot/dts/zynq-ebaz4205.dts')
-rw-r--r--arch/arm/boot/dts/zynq-ebaz4205.dts12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/zynq-ebaz4205.dts b/arch/arm/boot/dts/zynq-ebaz4205.dts
index b0b836aedd76..53fa6dbfd8fd 100644
--- a/arch/arm/boot/dts/zynq-ebaz4205.dts
+++ b/arch/arm/boot/dts/zynq-ebaz4205.dts
@@ -48,6 +48,14 @@
pinctrl-0 = <&pinctrl_gpio0_default>;
};
+&nfc0 {
+ status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ };
+};
+
&pinctrl0 {
pinctrl_gpio0_default: gpio0-default {
mux {
@@ -118,6 +126,10 @@
};
};
+&smcc {
+ status = "okay";
+};
+
&sdhci0 {
status = "okay";
disable-wp;