diff options
| author | Daniel Palmer <daniel@0x0f.com> | 2021-02-23 15:18:25 +0900 |
|---|---|---|
| committer | Romain Perier <romain.perier@gmail.com> | 2022-02-16 19:16:33 +0100 |
| commit | 6979b5fedb92c2e8f9aa7636cea1d2cb655f6f8d (patch) | |
| tree | 26021c16e3d5ebc809594449c5215f73fadc9d77 /arch/arm/boot/dts | |
| parent | c952e5075de1f76e092bc780503ebc5cb8222a01 (diff) | |
ARM: mstar: Add cpupll to base dtsi
All MStar/SigmaStar ARMv7 SoCs have the CPU PLL at the same
place so add it to the base dtsi.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Reviewed-by: Romain Perier <romain.perier@gmail.com>
Diffstat (limited to 'arch/arm/boot/dts')
| -rw-r--r-- | arch/arm/boot/dts/mstar-v7.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 89ebfe4f29da..2249faaa3aa7 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -155,6 +155,13 @@ clocks = <&xtal>; }; + cpupll: cpupll@206400 { + compatible = "mstar,msc313-cpupll"; + reg = <0x206400 0x200>; + #clock-cells = <0>; + clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>; + }; + gpio: gpio@207800 { #gpio-cells = <2>; reg = <0x207800 0x200>; |