diff options
| author | Biju Das <biju.das@bp.renesas.com> | 2018-11-28 16:38:28 +0000 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2018-12-04 06:21:13 -0800 |
| commit | eddcbe813dd3c8247840859bf4d04b3423d35f8f (patch) | |
| tree | 674cdb062e783161c528926cf2cb0a743cd490cf /arch/arm/boot/dts | |
| parent | 10fabcb817c5e37aeb8a1b79a95468c8df45898c (diff) | |
ARM: dts: r8a7744: Add VSP support
Add VSP support to SoC DT.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts')
| -rw-r--r-- | arch/arm/boot/dts/r8a7744.dtsi | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 094e1c4107e9..be84400c08ad 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -1367,6 +1367,33 @@ resets = <&cpg 408>; }; + vsp@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 131>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 131>; + }; + + vsp@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 128>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 128>; + }; + + vsp@fe938000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe938000 0 0x8000>; + interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 127>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 127>; + }; + du: display@feb00000 { reg = <0 0xfeb00000 0 0x40000>, <0 0xfeb90000 0 0x1c>; |